Ver Structural Verilog Compiler

One of the included examples showing a visual example of the output of Cyco, the cycle-simulation compiler when simulating a line-drawing unit. Its netlist was converted into levelized C code that executes in real-time.

Click here to download Ver-1.0.17 for Unix.
Click here to view a draft version of the docs for just the compiler itself and not the support packages.
Click here to view the change log for all of the included packages.
Click here to view supplemental notes for this distribution.
Click here to see GTKWave in action.

Hey Peoples!

Welcome to Ver Structural Verilog Compiler v1.0.17! I created this because I saw a need for a small portable Verilog compiler that doesn't have the sourcecode size limits of the VeriWell training simulator. Note that this is a *structural* compiler. Behaviorals (initial/always) are not supported in the compiler's parser yet. It's planned, but I don't know when I'll get around to writing that part. I'm tossing around the possibility of *not* including it and going the "add on module" route instead (i.e., using C programs that interface with the simulator). It's much faster and it's probably the way to go since the cycle simulator compiler (Cyco) generates C code anyway.

Look in the "examples" directory to get an idea of what the compiler can do. Any peculiarities in syntax will be noted in comment lines in the sourcecode. For the most part, any minor limitations will be noted in comment blocks in the sourcecode. I still have to work on making the parser a little more flexible like "really" allowing parameters and things like that.

The event simulator bundled with this is from the VHDL simulator VSIM from the University of Pittsburgh. As its authors say:

	This software is distributed on an as-is basis with no
	warranty implied or intended.  No author or distributor
	takes responsibility to anyone regarding its use of or
	suitability. 

	The software may be distributed and modified freely for
	academic and other non-commercial use but may NOT be
	utilized or included in whole or part within any
	commercial product.

Anna, the wave analyzer contains huge chunks of code from the IRSIM simulator. (The graphical front end was ripped from IRSIM and adapted for aet [all events trace] viewing.) As such, most of Anna is copyright by Stanford University. Most of my development is done under NetBSD Amiga, Linux on the PC, and AIX on the RS/6000, so Anna should more or less work on those three platforms. Any misbehaving can be traced to the event.c file. If all options fail in event.c and Anna still doesn't work, try to use BSD semantics for the signal handling as I do for Linux. (See the __linux__ ifdef's in event.c.)

As far as the ver directory goes, you can do with it whatever you feel like. But if you do anything interesting, please let me know. I'm just curious, that's all.

Well, that's about it for now. 1.0 is finally here now that GTKWave has been finished (all that remains is additional loaders and ergonomic stuff). Have fun!

05feb99 bybell@daggit.pagecreator.com / bybell@xxedgexx.com / bybell@vnet.ibm.com