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asix-sigma.c
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00001 /*
00002  * This file is part of the sigrok project.
00003  *
00004  * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
00005  * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
00006  * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
00007  *
00008  * This program is free software: you can redistribute it and/or modify
00009  * it under the terms of the GNU General Public License as published by
00010  * the Free Software Foundation, either version 3 of the License, or
00011  * (at your option) any later version.
00012  *
00013  * This program is distributed in the hope that it will be useful,
00014  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016  * GNU General Public License for more details.
00017  *
00018  * You should have received a copy of the GNU General Public License
00019  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
00020  */
00021 
00022 /*
00023  * ASIX SIGMA/SIGMA2 logic analyzer driver
00024  */
00025 
00026 #include <glib.h>
00027 #include <glib/gstdio.h>
00028 #include <ftdi.h>
00029 #include <string.h>
00030 #include "sigrok.h"
00031 #include "sigrok-internal.h"
00032 #include "asix-sigma.h"
00033 
00034 #define USB_VENDOR                      0xa600
00035 #define USB_PRODUCT                     0xa000
00036 #define USB_DESCRIPTION                 "ASIX SIGMA"
00037 #define USB_VENDOR_NAME                 "ASIX"
00038 #define USB_MODEL_NAME                  "SIGMA"
00039 #define USB_MODEL_VERSION               ""
00040 #define TRIGGER_TYPES                   "rf10"
00041 #define NUM_PROBES                      16
00042 
00043 static GSList *dev_insts = NULL;
00044 
00045 static uint64_t supported_samplerates[] = {
00046         SR_KHZ(200),
00047         SR_KHZ(250),
00048         SR_KHZ(500),
00049         SR_MHZ(1),
00050         SR_MHZ(5),
00051         SR_MHZ(10),
00052         SR_MHZ(25),
00053         SR_MHZ(50),
00054         SR_MHZ(100),
00055         SR_MHZ(200),
00056         0,
00057 };
00058 
00059 /*
00060  * Probe numbers seem to go from 1-16, according to this image:
00061  * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
00062  * (the cable has two additional GND pins, and a TI and TO pin)
00063  */
00064 static const char *probe_names[NUM_PROBES + 1] = {
00065         "1",
00066         "2",
00067         "3",
00068         "4",
00069         "5",
00070         "6",
00071         "7",
00072         "8",
00073         "9",
00074         "10",
00075         "11",
00076         "12",
00077         "13",
00078         "14",
00079         "15",
00080         "16",
00081         NULL,
00082 };
00083 
00084 static struct sr_samplerates samplerates = {
00085         0,
00086         0,
00087         0,
00088         supported_samplerates,
00089 };
00090 
00091 static int hwcaps[] = {
00092         SR_HWCAP_LOGIC_ANALYZER,
00093         SR_HWCAP_SAMPLERATE,
00094         SR_HWCAP_CAPTURE_RATIO,
00095         SR_HWCAP_PROBECONFIG,
00096 
00097         SR_HWCAP_LIMIT_MSEC,
00098         0,
00099 };
00100 
00101 /* Force the FPGA to reboot. */
00102 static uint8_t suicide[] = {
00103         0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
00104 };
00105 
00106 /* Prepare to upload firmware (FPGA specific). */
00107 static uint8_t init[] = {
00108         0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
00109 };
00110 
00111 /* Initialize the logic analyzer mode. */
00112 static uint8_t logic_mode_start[] = {
00113         0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
00114         0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
00115 };
00116 
00117 static const char *firmware_files[] = {
00118         "asix-sigma-50.fw",     /* 50 MHz, supports 8 bit fractions */
00119         "asix-sigma-100.fw",    /* 100 MHz */
00120         "asix-sigma-200.fw",    /* 200 MHz */
00121         "asix-sigma-50sync.fw", /* Synchronous clock from pin */
00122         "asix-sigma-phasor.fw", /* Frequency counter */
00123 };
00124 
00125 static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
00126 
00127 static int sigma_read(void *buf, size_t size, struct context *ctx)
00128 {
00129         int ret;
00130 
00131         ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
00132         if (ret < 0) {
00133                 sr_err("sigma: ftdi_read_data failed: %s",
00134                        ftdi_get_error_string(&ctx->ftdic));
00135         }
00136 
00137         return ret;
00138 }
00139 
00140 static int sigma_write(void *buf, size_t size, struct context *ctx)
00141 {
00142         int ret;
00143 
00144         ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
00145         if (ret < 0) {
00146                 sr_err("sigma: ftdi_write_data failed: %s",
00147                        ftdi_get_error_string(&ctx->ftdic));
00148         } else if ((size_t) ret != size) {
00149                 sr_err("sigma: ftdi_write_data did not complete write.");
00150         }
00151 
00152         return ret;
00153 }
00154 
00155 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
00156                                 struct context *ctx)
00157 {
00158         size_t i;
00159         uint8_t buf[len + 2];
00160         int idx = 0;
00161 
00162         buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
00163         buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
00164 
00165         for (i = 0; i < len; ++i) {
00166                 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
00167                 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
00168         }
00169 
00170         return sigma_write(buf, idx, ctx);
00171 }
00172 
00173 static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
00174 {
00175         return sigma_write_register(reg, &value, 1, ctx);
00176 }
00177 
00178 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
00179                                struct context *ctx)
00180 {
00181         uint8_t buf[3];
00182 
00183         buf[0] = REG_ADDR_LOW | (reg & 0xf);
00184         buf[1] = REG_ADDR_HIGH | (reg >> 4);
00185         buf[2] = REG_READ_ADDR;
00186 
00187         sigma_write(buf, sizeof(buf), ctx);
00188 
00189         return sigma_read(data, len, ctx);
00190 }
00191 
00192 static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
00193 {
00194         uint8_t value;
00195 
00196         if (1 != sigma_read_register(reg, &value, 1, ctx)) {
00197                 sr_err("sigma: sigma_get_register: 1 byte expected");
00198                 return 0;
00199         }
00200 
00201         return value;
00202 }
00203 
00204 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
00205                           struct context *ctx)
00206 {
00207         uint8_t buf[] = {
00208                 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
00209 
00210                 REG_READ_ADDR | NEXT_REG,
00211                 REG_READ_ADDR | NEXT_REG,
00212                 REG_READ_ADDR | NEXT_REG,
00213                 REG_READ_ADDR | NEXT_REG,
00214                 REG_READ_ADDR | NEXT_REG,
00215                 REG_READ_ADDR | NEXT_REG,
00216         };
00217         uint8_t result[6];
00218 
00219         sigma_write(buf, sizeof(buf), ctx);
00220 
00221         sigma_read(result, sizeof(result), ctx);
00222 
00223         *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
00224         *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
00225 
00226         /* Not really sure why this must be done, but according to spec. */
00227         if ((--*stoppos & 0x1ff) == 0x1ff)
00228                 stoppos -= 64;
00229 
00230         if ((*--triggerpos & 0x1ff) == 0x1ff)
00231                 triggerpos -= 64;
00232 
00233         return 1;
00234 }
00235 
00236 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
00237                            uint8_t *data, struct context *ctx)
00238 {
00239         size_t i;
00240         uint8_t buf[4096];
00241         int idx = 0;
00242 
00243         /* Send the startchunk. Index start with 1. */
00244         buf[0] = startchunk >> 8;
00245         buf[1] = startchunk & 0xff;
00246         sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
00247 
00248         /* Read the DRAM. */
00249         buf[idx++] = REG_DRAM_BLOCK;
00250         buf[idx++] = REG_DRAM_WAIT_ACK;
00251 
00252         for (i = 0; i < numchunks; ++i) {
00253                 /* Alternate bit to copy from DRAM to cache. */
00254                 if (i != (numchunks - 1))
00255                         buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
00256 
00257                 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
00258 
00259                 if (i != (numchunks - 1))
00260                         buf[idx++] = REG_DRAM_WAIT_ACK;
00261         }
00262 
00263         sigma_write(buf, idx, ctx);
00264 
00265         return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
00266 }
00267 
00268 /* Upload trigger look-up tables to Sigma. */
00269 static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
00270 {
00271         int i;
00272         uint8_t tmp[2];
00273         uint16_t bit;
00274 
00275         /* Transpose the table and send to Sigma. */
00276         for (i = 0; i < 16; ++i) {
00277                 bit = 1 << i;
00278 
00279                 tmp[0] = tmp[1] = 0;
00280 
00281                 if (lut->m2d[0] & bit)
00282                         tmp[0] |= 0x01;
00283                 if (lut->m2d[1] & bit)
00284                         tmp[0] |= 0x02;
00285                 if (lut->m2d[2] & bit)
00286                         tmp[0] |= 0x04;
00287                 if (lut->m2d[3] & bit)
00288                         tmp[0] |= 0x08;
00289 
00290                 if (lut->m3 & bit)
00291                         tmp[0] |= 0x10;
00292                 if (lut->m3s & bit)
00293                         tmp[0] |= 0x20;
00294                 if (lut->m4 & bit)
00295                         tmp[0] |= 0x40;
00296 
00297                 if (lut->m0d[0] & bit)
00298                         tmp[1] |= 0x01;
00299                 if (lut->m0d[1] & bit)
00300                         tmp[1] |= 0x02;
00301                 if (lut->m0d[2] & bit)
00302                         tmp[1] |= 0x04;
00303                 if (lut->m0d[3] & bit)
00304                         tmp[1] |= 0x08;
00305 
00306                 if (lut->m1d[0] & bit)
00307                         tmp[1] |= 0x10;
00308                 if (lut->m1d[1] & bit)
00309                         tmp[1] |= 0x20;
00310                 if (lut->m1d[2] & bit)
00311                         tmp[1] |= 0x40;
00312                 if (lut->m1d[3] & bit)
00313                         tmp[1] |= 0x80;
00314 
00315                 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
00316                                      ctx);
00317                 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
00318         }
00319 
00320         /* Send the parameters */
00321         sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
00322                              sizeof(lut->params), ctx);
00323 
00324         return SR_OK;
00325 }
00326 
00327 /* Generate the bitbang stream for programming the FPGA. */
00328 static int bin2bitbang(const char *filename,
00329                        unsigned char **buf, size_t *buf_size)
00330 {
00331         FILE *f;
00332         unsigned long file_size;
00333         unsigned long offset = 0;
00334         unsigned char *p;
00335         uint8_t *firmware;
00336         unsigned long fwsize = 0;
00337         const int buffer_size = 65536;
00338         size_t i;
00339         int c, bit, v;
00340         uint32_t imm = 0x3f6df2ab;
00341 
00342         f = g_fopen(filename, "rb");
00343         if (!f) {
00344                 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
00345                 return SR_ERR;
00346         }
00347 
00348         if (-1 == fseek(f, 0, SEEK_END)) {
00349                 sr_err("sigma: fseek on %s failed", filename);
00350                 fclose(f);
00351                 return SR_ERR;
00352         }
00353 
00354         file_size = ftell(f);
00355 
00356         fseek(f, 0, SEEK_SET);
00357 
00358         if (!(firmware = g_try_malloc(buffer_size))) {
00359                 sr_err("sigma: %s: firmware malloc failed", __func__);
00360                 fclose(f);
00361                 return SR_ERR_MALLOC;
00362         }
00363 
00364         while ((c = getc(f)) != EOF) {
00365                 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
00366                 firmware[fwsize++] = c ^ imm;
00367         }
00368         fclose(f);
00369 
00370         if(fwsize != file_size) {
00371             sr_err("sigma: %s: Error reading firmware", filename);
00372             fclose(f);
00373             g_free(firmware);
00374             return SR_ERR;
00375         }
00376 
00377         *buf_size = fwsize * 2 * 8;
00378 
00379         *buf = p = (unsigned char *)g_try_malloc(*buf_size);
00380         if (!p) {
00381                 sr_err("sigma: %s: buf/p malloc failed", __func__);
00382                 g_free(firmware);
00383                 return SR_ERR_MALLOC;
00384         }
00385 
00386         for (i = 0; i < fwsize; ++i) {
00387                 for (bit = 7; bit >= 0; --bit) {
00388                         v = firmware[i] & 1 << bit ? 0x40 : 0x00;
00389                         p[offset++] = v | 0x01;
00390                         p[offset++] = v;
00391                 }
00392         }
00393 
00394         g_free(firmware);
00395 
00396         if (offset != *buf_size) {
00397                 g_free(*buf);
00398                 sr_err("sigma: Error reading firmware %s "
00399                        "offset=%ld, file_size=%ld, buf_size=%zd.",
00400                        filename, offset, file_size, *buf_size);
00401 
00402                 return SR_ERR;
00403         }
00404 
00405         return SR_OK;
00406 }
00407 
00408 static int hw_init(const char *devinfo)
00409 {
00410         struct sr_dev_inst *sdi;
00411         struct context *ctx;
00412         struct ftdi_device_list *devlist;
00413         char serial_txt[10];
00414         uint32_t serial;
00415 
00416         /* Avoid compiler warnings. */
00417         (void)devinfo;
00418 
00419         if (!(ctx = g_try_malloc(sizeof(struct context)))) {
00420                 sr_err("sigma: %s: ctx malloc failed", __func__);
00421                 return SR_ERR_MALLOC;
00422         }
00423 
00424         ftdi_init(&ctx->ftdic);
00425 
00426         /* Look for SIGMAs. */
00427 
00428         if (ftdi_usb_find_all(&ctx->ftdic, &devlist,
00429             USB_VENDOR, USB_PRODUCT) <= 0)
00430                 goto free;
00431 
00432         /* Make sure it's a version 1 or 2 SIGMA. */
00433         ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
00434                              serial_txt, sizeof(serial_txt));
00435         sscanf(serial_txt, "%x", &serial);
00436 
00437         if (serial < 0xa6010000 || serial > 0xa602ffff) {
00438                 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
00439                        "in this version of sigrok.");
00440                 goto free;
00441         }
00442 
00443         sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
00444 
00445         ctx->cur_samplerate = 0;
00446         ctx->period_ps = 0;
00447         ctx->limit_msec = 0;
00448         ctx->cur_firmware = -1;
00449         ctx->num_probes = 0;
00450         ctx->samples_per_event = 0;
00451         ctx->capture_ratio = 50;
00452         ctx->use_triggers = 0;
00453 
00454         /* Register SIGMA device. */
00455         if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
00456                                     USB_MODEL_NAME, USB_MODEL_VERSION))) {
00457                 sr_err("sigma: %s: sdi was NULL", __func__);
00458                 goto free;
00459         }
00460 
00461         sdi->priv = ctx;
00462 
00463         dev_insts = g_slist_append(dev_insts, sdi);
00464 
00465         /* We will open the device again when we need it. */
00466         ftdi_list_free(&devlist);
00467 
00468         return 1;
00469 
00470 free:
00471         g_free(ctx);
00472         return 0;
00473 }
00474 
00475 static int upload_firmware(int firmware_idx, struct context *ctx)
00476 {
00477         int ret;
00478         unsigned char *buf;
00479         unsigned char pins;
00480         size_t buf_size;
00481         unsigned char result[32];
00482         char firmware_path[128];
00483 
00484         /* Make sure it's an ASIX SIGMA. */
00485         if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
00486                 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
00487                 sr_err("sigma: ftdi_usb_open failed: %s",
00488                        ftdi_get_error_string(&ctx->ftdic));
00489                 return 0;
00490         }
00491 
00492         if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
00493                 sr_err("sigma: ftdi_set_bitmode failed: %s",
00494                        ftdi_get_error_string(&ctx->ftdic));
00495                 return 0;
00496         }
00497 
00498         /* Four times the speed of sigmalogan - Works well. */
00499         if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
00500                 sr_err("sigma: ftdi_set_baudrate failed: %s",
00501                        ftdi_get_error_string(&ctx->ftdic));
00502                 return 0;
00503         }
00504 
00505         /* Force the FPGA to reboot. */
00506         sigma_write(suicide, sizeof(suicide), ctx);
00507         sigma_write(suicide, sizeof(suicide), ctx);
00508         sigma_write(suicide, sizeof(suicide), ctx);
00509         sigma_write(suicide, sizeof(suicide), ctx);
00510 
00511         /* Prepare to upload firmware (FPGA specific). */
00512         sigma_write(init, sizeof(init), ctx);
00513 
00514         ftdi_usb_purge_buffers(&ctx->ftdic);
00515 
00516         /* Wait until the FPGA asserts INIT_B. */
00517         while (1) {
00518                 ret = sigma_read(result, 1, ctx);
00519                 if (result[0] & 0x20)
00520                         break;
00521         }
00522 
00523         /* Prepare firmware. */
00524         snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
00525                  firmware_files[firmware_idx]);
00526 
00527         if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
00528                 sr_err("sigma: An error occured while reading the firmware: %s",
00529                        firmware_path);
00530                 return ret;
00531         }
00532 
00533         /* Upload firmare. */
00534         sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
00535         sigma_write(buf, buf_size, ctx);
00536 
00537         g_free(buf);
00538 
00539         if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
00540                 sr_err("sigma: ftdi_set_bitmode failed: %s",
00541                        ftdi_get_error_string(&ctx->ftdic));
00542                 return SR_ERR;
00543         }
00544 
00545         ftdi_usb_purge_buffers(&ctx->ftdic);
00546 
00547         /* Discard garbage. */
00548         while (1 == sigma_read(&pins, 1, ctx))
00549                 ;
00550 
00551         /* Initialize the logic analyzer mode. */
00552         sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
00553 
00554         /* Expect a 3 byte reply. */
00555         ret = sigma_read(result, 3, ctx);
00556         if (ret != 3 ||
00557             result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
00558                 sr_err("sigma: Configuration failed. Invalid reply received.");
00559                 return SR_ERR;
00560         }
00561 
00562         ctx->cur_firmware = firmware_idx;
00563 
00564         sr_info("sigma: Firmware uploaded");
00565 
00566         return SR_OK;
00567 }
00568 
00569 static int hw_dev_open(int dev_index)
00570 {
00571         struct sr_dev_inst *sdi;
00572         struct context *ctx;
00573         int ret;
00574 
00575         if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
00576                 return SR_ERR;
00577 
00578         ctx = sdi->priv;
00579 
00580         /* Make sure it's an ASIX SIGMA. */
00581         if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
00582                 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
00583 
00584                 sr_err("sigma: ftdi_usb_open failed: %s",
00585                        ftdi_get_error_string(&ctx->ftdic));
00586 
00587                 return 0;
00588         }
00589 
00590         sdi->status = SR_ST_ACTIVE;
00591 
00592         return SR_OK;
00593 }
00594 
00595 static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
00596 {
00597         int i, ret;
00598         struct context *ctx = sdi->priv;
00599 
00600         for (i = 0; supported_samplerates[i]; i++) {
00601                 if (supported_samplerates[i] == samplerate)
00602                         break;
00603         }
00604         if (supported_samplerates[i] == 0)
00605                 return SR_ERR_SAMPLERATE;
00606 
00607         if (samplerate <= SR_MHZ(50)) {
00608                 ret = upload_firmware(0, ctx);
00609                 ctx->num_probes = 16;
00610         }
00611         if (samplerate == SR_MHZ(100)) {
00612                 ret = upload_firmware(1, ctx);
00613                 ctx->num_probes = 8;
00614         }
00615         else if (samplerate == SR_MHZ(200)) {
00616                 ret = upload_firmware(2, ctx);
00617                 ctx->num_probes = 4;
00618         }
00619 
00620         ctx->cur_samplerate = samplerate;
00621         ctx->period_ps = 1000000000000 / samplerate;
00622         ctx->samples_per_event = 16 / ctx->num_probes;
00623         ctx->state.state = SIGMA_IDLE;
00624 
00625         return ret;
00626 }
00627 
00628 /*
00629  * In 100 and 200 MHz mode, only a single pin rising/falling can be
00630  * set as trigger. In other modes, two rising/falling triggers can be set,
00631  * in addition to value/mask trigger for any number of probes.
00632  *
00633  * The Sigma supports complex triggers using boolean expressions, but this
00634  * has not been implemented yet.
00635  */
00636 static int configure_probes(struct sr_dev_inst *sdi, GSList *probes)
00637 {
00638         struct context *ctx = sdi->priv;
00639         struct sr_probe *probe;
00640         GSList *l;
00641         int trigger_set = 0;
00642         int probebit;
00643 
00644         memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
00645 
00646         for (l = probes; l; l = l->next) {
00647                 probe = (struct sr_probe *)l->data;
00648                 probebit = 1 << (probe->index - 1);
00649 
00650                 if (!probe->enabled || !probe->trigger)
00651                         continue;
00652 
00653                 if (ctx->cur_samplerate >= SR_MHZ(100)) {
00654                         /* Fast trigger support. */
00655                         if (trigger_set) {
00656                                 sr_err("sigma: ASIX SIGMA only supports a single "
00657                                        "pin trigger in 100 and 200MHz mode.");
00658                                 return SR_ERR;
00659                         }
00660                         if (probe->trigger[0] == 'f')
00661                                 ctx->trigger.fallingmask |= probebit;
00662                         else if (probe->trigger[0] == 'r')
00663                                 ctx->trigger.risingmask |= probebit;
00664                         else {
00665                                 sr_err("sigma: ASIX SIGMA only supports "
00666                                        "rising/falling trigger in 100 "
00667                                        "and 200MHz mode.");
00668                                 return SR_ERR;
00669                         }
00670 
00671                         ++trigger_set;
00672                 } else {
00673                         /* Simple trigger support (event). */
00674                         if (probe->trigger[0] == '1') {
00675                                 ctx->trigger.simplevalue |= probebit;
00676                                 ctx->trigger.simplemask |= probebit;
00677                         }
00678                         else if (probe->trigger[0] == '0') {
00679                                 ctx->trigger.simplevalue &= ~probebit;
00680                                 ctx->trigger.simplemask |= probebit;
00681                         }
00682                         else if (probe->trigger[0] == 'f') {
00683                                 ctx->trigger.fallingmask |= probebit;
00684                                 ++trigger_set;
00685                         }
00686                         else if (probe->trigger[0] == 'r') {
00687                                 ctx->trigger.risingmask |= probebit;
00688                                 ++trigger_set;
00689                         }
00690 
00691                         /*
00692                          * Actually, Sigma supports 2 rising/falling triggers,
00693                          * but they are ORed and the current trigger syntax
00694                          * does not permit ORed triggers.
00695                          */
00696                         if (trigger_set > 1) {
00697                                 sr_err("sigma: ASIX SIGMA only supports 1 "
00698                                        "rising/falling triggers.");
00699                                 return SR_ERR;
00700                         }
00701                 }
00702 
00703                 if (trigger_set)
00704                         ctx->use_triggers = 1;
00705         }
00706 
00707         return SR_OK;
00708 }
00709 
00710 static int hw_dev_close(int dev_index)
00711 {
00712         struct sr_dev_inst *sdi;
00713         struct context *ctx;
00714 
00715         if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
00716                 sr_err("sigma: %s: sdi was NULL", __func__);
00717                 return SR_ERR_BUG;
00718         }
00719 
00720         if (!(ctx = sdi->priv)) {
00721                 sr_err("sigma: %s: sdi->priv was NULL", __func__);
00722                 return SR_ERR_BUG;
00723         }
00724 
00725         /* TODO */
00726         if (sdi->status == SR_ST_ACTIVE)
00727                 ftdi_usb_close(&ctx->ftdic);
00728 
00729         sdi->status = SR_ST_INACTIVE;
00730 
00731         return SR_OK;
00732 }
00733 
00734 static int hw_cleanup(void)
00735 {
00736         GSList *l;
00737         struct sr_dev_inst *sdi;
00738         int ret = SR_OK;
00739 
00740         /* Properly close all devices. */
00741         for (l = dev_insts; l; l = l->next) {
00742                 if (!(sdi = l->data)) {
00743                         /* Log error, but continue cleaning up the rest. */
00744                         sr_err("sigma: %s: sdi was NULL, continuing", __func__);
00745                         ret = SR_ERR_BUG;
00746                         continue;
00747                 }
00748                 sr_dev_inst_free(sdi);
00749         }
00750         g_slist_free(dev_insts);
00751         dev_insts = NULL;
00752 
00753         return ret;
00754 }
00755 
00756 static void *hw_dev_info_get(int dev_index, int dev_info_id)
00757 {
00758         struct sr_dev_inst *sdi;
00759         struct context *ctx;
00760         void *info = NULL;
00761 
00762         if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
00763                 sr_err("sigma: %s: sdi was NULL", __func__);
00764                 return NULL;
00765         }
00766 
00767         ctx = sdi->priv;
00768 
00769         switch (dev_info_id) {
00770         case SR_DI_INST:
00771                 info = sdi;
00772                 break;
00773         case SR_DI_NUM_PROBES:
00774                 info = GINT_TO_POINTER(NUM_PROBES);
00775                 break;
00776         case SR_DI_PROBE_NAMES:
00777                 info = probe_names;
00778                 break;
00779         case SR_DI_SAMPLERATES:
00780                 info = &samplerates;
00781                 break;
00782         case SR_DI_TRIGGER_TYPES:
00783                 info = (char *)TRIGGER_TYPES;
00784                 break;
00785         case SR_DI_CUR_SAMPLERATE:
00786                 info = &ctx->cur_samplerate;
00787                 break;
00788         }
00789 
00790         return info;
00791 }
00792 
00793 static int hw_dev_status_get(int dev_index)
00794 {
00795         struct sr_dev_inst *sdi;
00796 
00797         sdi = sr_dev_inst_get(dev_insts, dev_index);
00798         if (sdi)
00799                 return sdi->status;
00800         else
00801                 return SR_ST_NOT_FOUND;
00802 }
00803 
00804 static int *hw_hwcap_get_all(void)
00805 {
00806         return hwcaps;
00807 }
00808 
00809 static int hw_dev_config_set(int dev_index, int hwcap, void *value)
00810 {
00811         struct sr_dev_inst *sdi;
00812         struct context *ctx;
00813         int ret;
00814 
00815         if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
00816                 return SR_ERR;
00817 
00818         ctx = sdi->priv;
00819 
00820         if (hwcap == SR_HWCAP_SAMPLERATE) {
00821                 ret = set_samplerate(sdi, *(uint64_t *)value);
00822         } else if (hwcap == SR_HWCAP_PROBECONFIG) {
00823                 ret = configure_probes(sdi, value);
00824         } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
00825                 ctx->limit_msec = *(uint64_t *)value;
00826                 if (ctx->limit_msec > 0)
00827                         ret = SR_OK;
00828                 else
00829                         ret = SR_ERR;
00830         } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
00831                 ctx->capture_ratio = *(uint64_t *)value;
00832                 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
00833                         ret = SR_ERR;
00834                 else
00835                         ret = SR_OK;
00836         } else {
00837                 ret = SR_ERR;
00838         }
00839 
00840         return ret;
00841 }
00842 
00843 /* Software trigger to determine exact trigger position. */
00844 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
00845                               struct sigma_trigger *t)
00846 {
00847         int i;
00848 
00849         for (i = 0; i < 8; ++i) {
00850                 if (i > 0)
00851                         last_sample = samples[i-1];
00852 
00853                 /* Simple triggers. */
00854                 if ((samples[i] & t->simplemask) != t->simplevalue)
00855                         continue;
00856 
00857                 /* Rising edge. */
00858                 if ((last_sample & t->risingmask) != 0 || (samples[i] &
00859                     t->risingmask) != t->risingmask)
00860                         continue;
00861 
00862                 /* Falling edge. */
00863                 if ((last_sample & t->fallingmask) != t->fallingmask ||
00864                     (samples[i] & t->fallingmask) != 0)
00865                         continue;
00866 
00867                 break;
00868         }
00869 
00870         /* If we did not match, return original trigger pos. */
00871         return i & 0x7;
00872 }
00873 
00874 /*
00875  * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
00876  * Each event is 20ns apart, and can contain multiple samples.
00877  *
00878  * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
00879  * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
00880  * For 50 MHz and below, events contain one sample for each channel,
00881  * spread 20 ns apart.
00882  */
00883 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
00884                            uint16_t *lastsample, int triggerpos,
00885                            uint16_t limit_chunk, void *cb_data)
00886 {
00887         struct sr_dev_inst *sdi = cb_data;
00888         struct context *ctx = sdi->priv;
00889         uint16_t tsdiff, ts;
00890         uint16_t samples[65536 * ctx->samples_per_event];
00891         struct sr_datafeed_packet packet;
00892         struct sr_datafeed_logic logic;
00893         int i, j, k, l, numpad, tosend;
00894         size_t n = 0, sent = 0;
00895         int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
00896         uint16_t *event;
00897         uint16_t cur_sample;
00898         int triggerts = -1;
00899 
00900         /* Check if trigger is in this chunk. */
00901         if (triggerpos != -1) {
00902                 if (ctx->cur_samplerate <= SR_MHZ(50))
00903                         triggerpos -= EVENTS_PER_CLUSTER - 1;
00904 
00905                 if (triggerpos < 0)
00906                         triggerpos = 0;
00907 
00908                 /* Find in which cluster the trigger occured. */
00909                 triggerts = triggerpos / 7;
00910         }
00911 
00912         /* For each ts. */
00913         for (i = 0; i < 64; ++i) {
00914                 ts = *(uint16_t *) &buf[i * 16];
00915                 tsdiff = ts - *lastts;
00916                 *lastts = ts;
00917 
00918                 /* Decode partial chunk. */
00919                 if (limit_chunk && ts > limit_chunk)
00920                         return SR_OK;
00921 
00922                 /* Pad last sample up to current point. */
00923                 numpad = tsdiff * ctx->samples_per_event - clustersize;
00924                 if (numpad > 0) {
00925                         for (j = 0; j < numpad; ++j)
00926                                 samples[j] = *lastsample;
00927 
00928                         n = numpad;
00929                 }
00930 
00931                 /* Send samples between previous and this timestamp to sigrok. */
00932                 sent = 0;
00933                 while (sent < n) {
00934                         tosend = MIN(2048, n - sent);
00935 
00936                         packet.type = SR_DF_LOGIC;
00937                         packet.payload = &logic;
00938                         logic.length = tosend * sizeof(uint16_t);
00939                         logic.unitsize = 2;
00940                         logic.data = samples + sent;
00941                         sr_session_send(ctx->session_dev_id, &packet);
00942 
00943                         sent += tosend;
00944                 }
00945                 n = 0;
00946 
00947                 event = (uint16_t *) &buf[i * 16 + 2];
00948                 cur_sample = 0;
00949 
00950                 /* For each event in cluster. */
00951                 for (j = 0; j < 7; ++j) {
00952 
00953                         /* For each sample in event. */
00954                         for (k = 0; k < ctx->samples_per_event; ++k) {
00955                                 cur_sample = 0;
00956 
00957                                 /* For each probe. */
00958                                 for (l = 0; l < ctx->num_probes; ++l)
00959                                         cur_sample |= (!!(event[j] & (1 << (l *
00960                                            ctx->samples_per_event + k)))) << l;
00961 
00962                                 samples[n++] = cur_sample;
00963                         }
00964                 }
00965 
00966                 /* Send data up to trigger point (if triggered). */
00967                 sent = 0;
00968                 if (i == triggerts) {
00969                         /*
00970                          * Trigger is not always accurate to sample because of
00971                          * pipeline delay. However, it always triggers before
00972                          * the actual event. We therefore look at the next
00973                          * samples to pinpoint the exact position of the trigger.
00974                          */
00975                         tosend = get_trigger_offset(samples, *lastsample,
00976                                                     &ctx->trigger);
00977 
00978                         if (tosend > 0) {
00979                                 packet.type = SR_DF_LOGIC;
00980                                 packet.payload = &logic;
00981                                 logic.length = tosend * sizeof(uint16_t);
00982                                 logic.unitsize = 2;
00983                                 logic.data = samples;
00984                                 sr_session_send(ctx->session_dev_id, &packet);
00985 
00986                                 sent += tosend;
00987                         }
00988 
00989                         /* Only send trigger if explicitly enabled. */
00990                         if (ctx->use_triggers) {
00991                                 packet.type = SR_DF_TRIGGER;
00992                                 sr_session_send(ctx->session_dev_id, &packet);
00993                         }
00994                 }
00995 
00996                 /* Send rest of the chunk to sigrok. */
00997                 tosend = n - sent;
00998 
00999                 if (tosend > 0) {
01000                         packet.type = SR_DF_LOGIC;
01001                         packet.payload = &logic;
01002                         logic.length = tosend * sizeof(uint16_t);
01003                         logic.unitsize = 2;
01004                         logic.data = samples + sent;
01005                         sr_session_send(ctx->session_dev_id, &packet);
01006                 }
01007 
01008                 *lastsample = samples[n - 1];
01009         }
01010 
01011         return SR_OK;
01012 }
01013 
01014 static int receive_data(int fd, int revents, void *cb_data)
01015 {
01016         struct sr_dev_inst *sdi = cb_data;
01017         struct context *ctx = sdi->priv;
01018         struct sr_datafeed_packet packet;
01019         const int chunks_per_read = 32;
01020         unsigned char buf[chunks_per_read * CHUNK_SIZE];
01021         int bufsz, numchunks, i, newchunks;
01022         uint64_t running_msec;
01023         struct timeval tv;
01024 
01025         /* Avoid compiler warnings. */
01026         (void)fd;
01027         (void)revents;
01028 
01029         /* Get the current position. */
01030         sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
01031 
01032         numchunks = (ctx->state.stoppos + 511) / 512;
01033 
01034         if (ctx->state.state == SIGMA_IDLE)
01035                 return TRUE;
01036 
01037         if (ctx->state.state == SIGMA_CAPTURE) {
01038                 /* Check if the timer has expired, or memory is full. */
01039                 gettimeofday(&tv, 0);
01040                 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
01041                         (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
01042 
01043                 if (running_msec < ctx->limit_msec && numchunks < 32767)
01044                         return TRUE; /* While capturing... */
01045                 else
01046                         hw_dev_acquisition_stop(sdi->index, sdi);
01047 
01048         } else if (ctx->state.state == SIGMA_DOWNLOAD) {
01049                 if (ctx->state.chunks_downloaded >= numchunks) {
01050                         /* End of samples. */
01051                         packet.type = SR_DF_END;
01052                         sr_session_send(ctx->session_dev_id, &packet);
01053 
01054                         ctx->state.state = SIGMA_IDLE;
01055 
01056                         return TRUE;
01057                 }
01058 
01059                 newchunks = MIN(chunks_per_read,
01060                                 numchunks - ctx->state.chunks_downloaded);
01061 
01062                 sr_info("sigma: Downloading sample data: %.0f %%",
01063                         100.0 * ctx->state.chunks_downloaded / numchunks);
01064 
01065                 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
01066                                         newchunks, buf, ctx);
01067                 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
01068                 (void)bufsz;
01069 
01070                 /* Find first ts. */
01071                 if (ctx->state.chunks_downloaded == 0) {
01072                         ctx->state.lastts = *(uint16_t *) buf - 1;
01073                         ctx->state.lastsample = 0;
01074                 }
01075 
01076                 /* Decode chunks and send them to sigrok. */
01077                 for (i = 0; i < newchunks; ++i) {
01078                         int limit_chunk = 0;
01079 
01080                         /* The last chunk may potentially be only in part. */
01081                         if (ctx->state.chunks_downloaded == numchunks - 1) {
01082                                 /* Find the last valid timestamp */
01083                                 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
01084                         }
01085 
01086                         if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
01087                                 decode_chunk_ts(buf + (i * CHUNK_SIZE),
01088                                                 &ctx->state.lastts,
01089                                                 &ctx->state.lastsample,
01090                                                 ctx->state.triggerpos & 0x1ff,
01091                                                 limit_chunk, sdi);
01092                         else
01093                                 decode_chunk_ts(buf + (i * CHUNK_SIZE),
01094                                                 &ctx->state.lastts,
01095                                                 &ctx->state.lastsample,
01096                                                 -1, limit_chunk, sdi);
01097 
01098                         ++ctx->state.chunks_downloaded;
01099                 }
01100         }
01101 
01102         return TRUE;
01103 }
01104 
01105 /* Build a LUT entry used by the trigger functions. */
01106 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
01107 {
01108         int i, j, k, bit;
01109 
01110         /* For each quad probe. */
01111         for (i = 0; i < 4; ++i) {
01112                 entry[i] = 0xffff;
01113 
01114                 /* For each bit in LUT. */
01115                 for (j = 0; j < 16; ++j)
01116 
01117                         /* For each probe in quad. */
01118                         for (k = 0; k < 4; ++k) {
01119                                 bit = 1 << (i * 4 + k);
01120 
01121                                 /* Set bit in entry */
01122                                 if ((mask & bit) &&
01123                                     ((!(value & bit)) !=
01124                                     (!(j & (1 << k)))))
01125                                         entry[i] &= ~(1 << j);
01126                         }
01127         }
01128 }
01129 
01130 /* Add a logical function to LUT mask. */
01131 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
01132                                  int index, int neg, uint16_t *mask)
01133 {
01134         int i, j;
01135         int x[2][2], tmp, a, b, aset, bset, rset;
01136 
01137         memset(x, 0, 4 * sizeof(int));
01138 
01139         /* Trigger detect condition. */
01140         switch (oper) {
01141         case OP_LEVEL:
01142                 x[0][1] = 1;
01143                 x[1][1] = 1;
01144                 break;
01145         case OP_NOT:
01146                 x[0][0] = 1;
01147                 x[1][0] = 1;
01148                 break;
01149         case OP_RISE:
01150                 x[0][1] = 1;
01151                 break;
01152         case OP_FALL:
01153                 x[1][0] = 1;
01154                 break;
01155         case OP_RISEFALL:
01156                 x[0][1] = 1;
01157                 x[1][0] = 1;
01158                 break;
01159         case OP_NOTRISE:
01160                 x[1][1] = 1;
01161                 x[0][0] = 1;
01162                 x[1][0] = 1;
01163                 break;
01164         case OP_NOTFALL:
01165                 x[1][1] = 1;
01166                 x[0][0] = 1;
01167                 x[0][1] = 1;
01168                 break;
01169         case OP_NOTRISEFALL:
01170                 x[1][1] = 1;
01171                 x[0][0] = 1;
01172                 break;
01173         }
01174 
01175         /* Transpose if neg is set. */
01176         if (neg) {
01177                 for (i = 0; i < 2; ++i) {
01178                         for (j = 0; j < 2; ++j) {
01179                                 tmp = x[i][j];
01180                                 x[i][j] = x[1-i][1-j];
01181                                 x[1-i][1-j] = tmp;
01182                         }
01183                 }
01184         }
01185 
01186         /* Update mask with function. */
01187         for (i = 0; i < 16; ++i) {
01188                 a = (i >> (2 * index + 0)) & 1;
01189                 b = (i >> (2 * index + 1)) & 1;
01190 
01191                 aset = (*mask >> i) & 1;
01192                 bset = x[b][a];
01193 
01194                 if (func == FUNC_AND || func == FUNC_NAND)
01195                         rset = aset & bset;
01196                 else if (func == FUNC_OR || func == FUNC_NOR)
01197                         rset = aset | bset;
01198                 else if (func == FUNC_XOR || func == FUNC_NXOR)
01199                         rset = aset ^ bset;
01200 
01201                 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
01202                         rset = !rset;
01203 
01204                 *mask &= ~(1 << i);
01205 
01206                 if (rset)
01207                         *mask |= 1 << i;
01208         }
01209 }
01210 
01211 /*
01212  * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
01213  * simple pin change and state triggers. Only two transitions (rise/fall) can be
01214  * set at any time, but a full mask and value can be set (0/1).
01215  */
01216 static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
01217 {
01218         int i,j;
01219         uint16_t masks[2] = { 0, 0 };
01220 
01221         memset(lut, 0, sizeof(struct triggerlut));
01222 
01223         /* Contant for simple triggers. */
01224         lut->m4 = 0xa000;
01225 
01226         /* Value/mask trigger support. */
01227         build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
01228                         lut->m2d);
01229 
01230         /* Rise/fall trigger support. */
01231         for (i = 0, j = 0; i < 16; ++i) {
01232                 if (ctx->trigger.risingmask & (1 << i) ||
01233                     ctx->trigger.fallingmask & (1 << i))
01234                         masks[j++] = 1 << i;
01235         }
01236 
01237         build_lut_entry(masks[0], masks[0], lut->m0d);
01238         build_lut_entry(masks[1], masks[1], lut->m1d);
01239 
01240         /* Add glue logic */
01241         if (masks[0] || masks[1]) {
01242                 /* Transition trigger. */
01243                 if (masks[0] & ctx->trigger.risingmask)
01244                         add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
01245                 if (masks[0] & ctx->trigger.fallingmask)
01246                         add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
01247                 if (masks[1] & ctx->trigger.risingmask)
01248                         add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
01249                 if (masks[1] & ctx->trigger.fallingmask)
01250                         add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
01251         } else {
01252                 /* Only value/mask trigger. */
01253                 lut->m3 = 0xffff;
01254         }
01255 
01256         /* Triggertype: event. */
01257         lut->params.selres = 3;
01258 
01259         return SR_OK;
01260 }
01261 
01262 static int hw_dev_acquisition_start(int dev_index, void *cb_data)
01263 {
01264         struct sr_dev_inst *sdi;
01265         struct context *ctx;
01266         struct sr_datafeed_packet *packet;
01267         struct sr_datafeed_header *header;
01268         struct clockselect_50 clockselect;
01269         int frac, triggerpin, ret;
01270         uint8_t triggerselect;
01271         struct triggerinout triggerinout_conf;
01272         struct triggerlut lut;
01273 
01274         if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
01275                 return SR_ERR;
01276 
01277         ctx = sdi->priv;
01278 
01279         /* If the samplerate has not been set, default to 200 kHz. */
01280         if (ctx->cur_firmware == -1) {
01281                 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
01282                         return ret;
01283         }
01284 
01285         /* Enter trigger programming mode. */
01286         sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
01287 
01288         /* 100 and 200 MHz mode. */
01289         if (ctx->cur_samplerate >= SR_MHZ(100)) {
01290                 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
01291 
01292                 /* Find which pin to trigger on from mask. */
01293                 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
01294                         if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
01295                             (1 << triggerpin))
01296                                 break;
01297 
01298                 /* Set trigger pin and light LED on trigger. */
01299                 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
01300 
01301                 /* Default rising edge. */
01302                 if (ctx->trigger.fallingmask)
01303                         triggerselect |= 1 << 3;
01304 
01305         /* All other modes. */
01306         } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
01307                 build_basic_trigger(&lut, ctx);
01308 
01309                 sigma_write_trigger_lut(&lut, ctx);
01310 
01311                 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
01312         }
01313 
01314         /* Setup trigger in and out pins to default values. */
01315         memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
01316         triggerinout_conf.trgout_bytrigger = 1;
01317         triggerinout_conf.trgout_enable = 1;
01318 
01319         sigma_write_register(WRITE_TRIGGER_OPTION,
01320                              (uint8_t *) &triggerinout_conf,
01321                              sizeof(struct triggerinout), ctx);
01322 
01323         /* Go back to normal mode. */
01324         sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
01325 
01326         /* Set clock select register. */
01327         if (ctx->cur_samplerate == SR_MHZ(200))
01328                 /* Enable 4 probes. */
01329                 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
01330         else if (ctx->cur_samplerate == SR_MHZ(100))
01331                 /* Enable 8 probes. */
01332                 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
01333         else {
01334                 /*
01335                  * 50 MHz mode (or fraction thereof). Any fraction down to
01336                  * 50 MHz / 256 can be used, but is not supported by sigrok API.
01337                  */
01338                 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
01339 
01340                 clockselect.async = 0;
01341                 clockselect.fraction = frac;
01342                 clockselect.disabled_probes = 0;
01343 
01344                 sigma_write_register(WRITE_CLOCK_SELECT,
01345                                      (uint8_t *) &clockselect,
01346                                      sizeof(clockselect), ctx);
01347         }
01348 
01349         /* Setup maximum post trigger time. */
01350         sigma_set_register(WRITE_POST_TRIGGER,
01351                            (ctx->capture_ratio * 255) / 100, ctx);
01352 
01353         /* Start acqusition. */
01354         gettimeofday(&ctx->start_tv, 0);
01355         sigma_set_register(WRITE_MODE, 0x0d, ctx);
01356 
01357         ctx->session_dev_id = cb_data;
01358 
01359         if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
01360                 sr_err("sigma: %s: packet malloc failed.", __func__);
01361                 return SR_ERR_MALLOC;
01362         }
01363 
01364         if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
01365                 sr_err("sigma: %s: header malloc failed.", __func__);
01366                 return SR_ERR_MALLOC;
01367         }
01368 
01369         /* Add capture source. */
01370         sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
01371 
01372         /* Send header packet to the session bus. */
01373         packet->type = SR_DF_HEADER;
01374         packet->payload = header;
01375         header->feed_version = 1;
01376         gettimeofday(&header->starttime, NULL);
01377         header->samplerate = ctx->cur_samplerate;
01378         header->num_logic_probes = ctx->num_probes;
01379         sr_session_send(ctx->session_dev_id, packet);
01380         g_free(header);
01381         g_free(packet);
01382 
01383         ctx->state.state = SIGMA_CAPTURE;
01384 
01385         return SR_OK;
01386 }
01387 
01388 static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
01389 {
01390         struct sr_dev_inst *sdi;
01391         struct context *ctx;
01392         uint8_t modestatus;
01393 
01394         /* Avoid compiler warnings. */
01395         (void)cb_data;
01396 
01397         if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
01398                 sr_err("sigma: %s: sdi was NULL", __func__);
01399                 return SR_ERR_BUG;
01400         }
01401 
01402         if (!(ctx = sdi->priv)) {
01403                 sr_err("sigma: %s: sdi->priv was NULL", __func__);
01404                 return SR_ERR_BUG;
01405         }
01406 
01407         /* Stop acquisition. */
01408         sigma_set_register(WRITE_MODE, 0x11, ctx);
01409 
01410         /* Set SDRAM Read Enable. */
01411         sigma_set_register(WRITE_MODE, 0x02, ctx);
01412 
01413         /* Get the current position. */
01414         sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
01415 
01416         /* Check if trigger has fired. */
01417         modestatus = sigma_get_register(READ_MODE, ctx);
01418         if (modestatus & 0x20)
01419                 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
01420         else
01421                 ctx->state.triggerchunk = -1;
01422 
01423         ctx->state.chunks_downloaded = 0;
01424 
01425         ctx->state.state = SIGMA_DOWNLOAD;
01426 
01427         return SR_OK;
01428 }
01429 
01430 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
01431         .name = "asix-sigma",
01432         .longname = "ASIX SIGMA/SIGMA2",
01433         .api_version = 1,
01434         .init = hw_init,
01435         .cleanup = hw_cleanup,
01436         .dev_open = hw_dev_open,
01437         .dev_close = hw_dev_close,
01438         .dev_info_get = hw_dev_info_get,
01439         .dev_status_get = hw_dev_status_get,
01440         .hwcap_get_all = hw_hwcap_get_all,
01441         .dev_config_set = hw_dev_config_set,
01442         .dev_acquisition_start = hw_dev_acquisition_start,
01443         .dev_acquisition_stop = hw_dev_acquisition_stop,
01444 };
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