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00023 #ifndef MMU_H
00024 #define MMU_H
00025
00026 #include "sidplayfp/sidendian.h"
00027 #include "sidplayfp/siddefs.h"
00028 #include "sidplayfp/sidmemory.h"
00029
00030 #include "Banks/Bank.h"
00031 #include "Banks/IOBank.h"
00032 #include "Banks/SystemRAMBank.h"
00033 #include "Banks/SystemROMBanks.h"
00034 #include "Banks/ZeroRAMBank.h"
00035
00036 #include <string.h>
00037
00041 class MMU : public PLA, public sidmemory
00042 {
00043 private:
00044 EventContext &context;
00045
00047 bool loram, hiram, charen;
00048
00050 Bank* cpuReadMap[16];
00051
00053 Bank* cpuWriteMap[16];
00054
00056 Bank* ioBank;
00057
00059 KernalRomBank kernalRomBank;
00060
00062 BasicRomBank basicRomBank;
00063
00065 CharacterRomBank characterRomBank;
00066
00068 SystemRAMBank ramBank;
00069
00070 ZeroRAMBank zeroRAMBank;
00071
00072 private:
00073 void setCpuPort(int state);
00074 void updateMappingPHI2();
00075 uint8_t getLastReadByte() const { return 0; }
00076 event_clock_t getPhi2Time() const { return context.getTime(EVENT_CLOCK_PHI2); }
00077
00078 public:
00079 MMU(EventContext *context, Bank* ioBank);
00080 ~MMU () {}
00081
00082 void reset();
00083
00084 void setRoms(const uint8_t* kernal, const uint8_t* basic, const uint8_t* character)
00085 {
00086 kernalRomBank.set(kernal);
00087 basicRomBank.set(basic);
00088 characterRomBank.set(character);
00089 }
00090
00091
00092 uint8_t readMemByte(uint_least16_t addr) { return ramBank.peek(addr); }
00093 uint_least16_t readMemWord(uint_least16_t addr) { return endian_little16(ramBank.array()+addr); }
00094
00095 void writeMemByte(uint_least16_t addr, uint8_t value) { ramBank.poke(addr, value); }
00096 void writeMemWord(uint_least16_t addr, uint_least16_t value) { endian_little16(ramBank.array()+addr, value); }
00097
00098 void fillRam(uint_least16_t start, uint8_t value, unsigned int size)
00099 {
00100 memset(ramBank.array()+start, value, size);
00101 }
00102 void fillRam(uint_least16_t start, const uint8_t* source, unsigned int size)
00103 {
00104 memcpy(ramBank.array()+start, source, size);
00105 }
00106
00107
00108 void installResetHook(uint_least16_t addr) { kernalRomBank.installResetHook(addr); }
00109
00110 void installBasicTrap(uint_least16_t addr) { basicRomBank.installTrap(addr); }
00111
00112 void setBasicSubtune(uint8_t tune) { basicRomBank.setSubtune(tune); }
00113
00120 uint8_t cpuRead(uint_least16_t addr) const { return cpuReadMap[addr >> 12]->peek(addr); }
00121
00128 void cpuWrite(uint_least16_t addr, uint8_t data) { cpuWriteMap[addr >> 12]->poke(addr, data); }
00129 };
00130
00131 #endif