PIC18F67J50
CONFIG1L (address:0x01FFF8, mask:0xEF)
WDTEN -- Watchdog Timer Enable bit
WDTEN = OFF 0xFE WDT disabled (control is placed on SWDTEN bit).
WDTEN = ON 0xFF WDT enabled.
PLLDIV -- PLL Prescaler Selection bits
PLLDIV = 12 0xF1 Divide by 12 (48 MHz oscillator input).
PLLDIV = 10 0xF3 Divide by 10 (40 MHz oscillator input).
PLLDIV = 6 0xF5 Divide by 6 (24 MHz oscillator input).
PLLDIV = 5 0xF7 Divide by 5 (20 MHz oscillator input).
PLLDIV = 4 0xF9 Divide by 4 (16 MHz oscillator input).
PLLDIV = 3 0xFB Divide by 3 (12 MHz oscillator input).
PLLDIV = 2 0xFD Divide by 2 (8 MHz oscillator input).
PLLDIV = 1 0xFF No prescale (4 MHz oscillator input drives PLL directly).
STVREN -- Stack Overflow/Underflow Reset Enable bit
STVREN = OFF 0xDF Reset on stack overflow/underflow disabled.
STVREN = ON 0xFF Reset on stack overflow/underflow enabled.
XINST -- Extended Instruction Set Enable bit
XINST = OFF 0xBF Instruction set extension and Indexed Addressing mode disabled (Legacy mode).
XINST = ON 0xFF Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit
DEBUG = ON 0x7F Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF 0xFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins.
CONFIG1H (address:0x01FFF9, mask:0xF7)
CPUDIV -- CPU System Clock Postscaler
CPUDIV = OSC4_PLL6 0xFC CPU system clock divide by 6.
CPUDIV = OSC3_PLL3 0xFD CPU system clock divide by 3.
CPUDIV = OSC2_PLL2 0xFE CPU system clock divide by 2.
CPUDIV = OSC1 0xFF No CPU system clock divide.
CP0 -- Code Protection bit
CP0 = ON 0xFB Program memory is code-protected.
CP0 = OFF 0xFF Program memory is not code-protected.
CONFIG2L (address:0x01FFFA, mask:0xC7)
FOSC -- Oscillator Selection bits
FOSC = INTOSC 0xF8 INTOSC, Port function on RA6 and RA7.
FOSC = INTOSCO 0xF9 INTOSC, CLKO on RA6 and Port function on RA7.
FOSC = INTOSCPLL 0xFA INTOSC with PLL enabled, Port function on RA6 and RA7.
FOSC = INTOSCPLLO 0xFB INTOSC with PLL enabled, CLKO on RA6 and Port function on RA7.
FOSC = HS 0xFC HS oscillator, HS used by USB.
FOSC = HSPLL 0xFD HS oscillator, PLL enabled, HSPLL used by USB.
FOSC = EC 0xFE EC Oscillator with CLKO on RA6, EC used by USB.
FOSC = ECPLL 0xFF EC Oscillator with PLL, CLKO on RA6, ECPLL used by USB.
FCMEN -- Fail-Safe Clock Monitor Enable bit
FCMEN = OFF 0xBF Fail-Safe Clock Monitor disabled.
FCMEN = ON 0xFF Fail-Safe Clock Monitor enabled.
IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
IESO = OFF 0x7F Two-Speed Start-up disabled.
IESO = ON 0xFF Two-Speed Start-up enabled.
CONFIG2H (address:0x01FFFB, mask:0xFF)
WDTPS -- Watchdog Timer Postscaler Select bits
WDTPS = 1 0xF0 1:1.
WDTPS = 2 0xF1 1:2.
WDTPS = 4 0xF2 1:4.
WDTPS = 8 0xF3 1:8.
WDTPS = 16 0xF4 1:16.
WDTPS = 32 0xF5 1:32.
WDTPS = 64 0xF6 1:64.
WDTPS = 128 0xF7 1:128.
WDTPS = 256 0xF8 1:256.
WDTPS = 512 0xF9 1:512.
WDTPS = 1024 0xFA 1:1024.
WDTPS = 2048 0xFB 1:2048.
WDTPS = 4096 0xFC 1:4096.
WDTPS = 8192 0xFD 1:8192.
WDTPS = 16384 0xFE 1:16384.
WDTPS = 32768 0xFF 1:32768.
CONFIG3L (address:0x01FFFC, mask:0xF8)
CONFIG3H (address:0x01FFFD, mask:0xF9)
CCP2MX -- ECCP2 MUX bit
CCP2MX = ALTERNATE 0xFE ECCP2/P2A is multiplexed with RE7.
CCP2MX = DEFAULT 0xFF ECCP2/P2A is multiplexed with RC1.
MSSPMSK -- MSSP Address Masking Mode Select bit
MSSPMSK = MSK5 0xF7 5-Bit Address Masking mode enable.
MSSPMSK = MSK7 0xFF 7-Bit Address Masking mode enable.

This page generated automatically by the device-help.pl program (2012-11-26 09:26:01 UTC) from the 8bit_device.info file (rev: 1.10) of mpasmx and from the gputils source package (rev: svn 834). The mpasmx is included in the MPLAB X. The device-help.pl is included in the gputils source package.