PIC18F86J15
CONFIG1L (address:0x017FF8, mask:0xE1)
WDTEN -- Watchdog Timer Enable bit
WDTEN = OFF 0xFE WDT disabled (control is placed on SWDTEN bit).
WDTEN = ON 0xFF WDT enabled.
STVREN -- Stack Overflow/Underflow Reset Enable bit
STVREN = OFF 0xDF Reset on stack overflow/underflow disabled.
STVREN = ON 0xFF Reset on stack overflow/underflow enabled.
XINST -- Extended Instruction Set Enable bit
XINST = OFF 0xBF Instruction set extension and Indexed Addressing mode disabled (Legacy mode).
XINST = ON 0xFF Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit
DEBUG = ON 0x7F Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF 0xFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins.
CONFIG1H (address:0x017FF9, mask:0xF4)
CP0 -- Code Protection bit
CP0 = ON 0xFB Program memory is code-protected.
CP0 = OFF 0xFF Program memory is not code-protected.
CONFIG2L (address:0x017FFA, mask:0xC7)
FOSC -- Oscillator Selection bits
FOSC = HS 0xFC HS oscillator.
FOSC = HSPLL 0xFD HS oscillator, PLL enabled and under software control.
FOSC = EC 0xFE EC oscillator, CLKO function on OSC2.
FOSC = ECPLL 0xFF EC oscillator, PLL enabled and under software control, CLK function on OSC2.
FOSC2 -- Default/Reset System Clock Select bit
FOSC2 = OFF 0xFB INTRC enabled as system clock when OSCCON<1:0> = 00.
FOSC2 = ON 0xFF Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00.
FCMEN -- Fail-Safe Clock Monitor Enable
FCMEN = OFF 0xBF Fail-Safe Clock Monitor disabled.
FCMEN = ON 0xFF Fail-Safe Clock Monitor enabled.
IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
IESO = OFF 0x7F Two-Speed Start-up disabled.
IESO = ON 0xFF Two-Speed Start-up enabled.
CONFIG2H (address:0x017FFB, mask:0xFF)
WDTPS -- Watchdog Timer Postscaler Select bits
WDTPS = 1 0xF0 1:1.
WDTPS = 2 0xF1 1:2.
WDTPS = 4 0xF2 1:4.
WDTPS = 8 0xF3 1:8.
WDTPS = 16 0xF4 1:16.
WDTPS = 32 0xF5 1:32.
WDTPS = 64 0xF6 1:64.
WDTPS = 128 0xF7 1:128.
WDTPS = 256 0xF8 1:256.
WDTPS = 512 0xF9 1:512.
WDTPS = 1024 0xFA 1:1024.
WDTPS = 2048 0xFB 1:2048.
WDTPS = 4096 0xFC 1:4096.
WDTPS = 8192 0xFD 1:8192.
WDTPS = 16384 0xFE 1:16384.
WDTPS = 32768 0xFF 1:32768.
CONFIG3L (address:0x017FFC, mask:0xF8)
EASHFT -- External Address Bus Shift Enable bit
EASHFT = OFF 0xF7 Address shifting disabled, address on external bus reflects the PC value.
EASHFT = ON 0xFF Address shifting enabled, address on external bus is offset to start at 000000h.
MODE -- External Memory Bus
MODE = XM20 0xCF Extended Microcontroller mode - 20-bit Address mode.
MODE = XM16 0xDF Extended Microcontroller mode - 16-bit Address mode.
MODE = XM12 0xEF Extended Microcontroller mode - 12-bit Address mode.
MODE = MM 0xFF Microcontroller mode - External bus disabled.
BW -- Data Bus Width Select bit
BW = 8 0xBF 8-bit external bus mode.
BW = 16 0xFF 16-bit external bus mode.
WAIT -- External Bus Wait Enable bit
WAIT = ON 0x7F Wait states for operations on external memory bus enabled.
WAIT = OFF 0xFF Wait states for operations on external memory bus disabled.
CONFIG3H (address:0x017FFD, mask:0xF3)
CCP2MX -- ECCP2 MUX bit
CCP2MX = ALTERNATE 0xFE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode.
CCP2MX = DEFAULT 0xFF ECCP2/P2A is multiplexed with RC1.
ECCPMX -- ECCPx MUX bit
ECCPMX = ALTERNATE 0xFD ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4.
ECCPMX = DEFAULT 0xFF ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3.

This page generated automatically by the device-help.pl program (2012-11-26 09:26:01 UTC) from the 8bit_device.info file (rev: 1.10) of mpasmx and from the gputils source package (rev: svn 834). The mpasmx is included in the MPLAB X. The device-help.pl is included in the gputils source package.