PIC18F66K90 |
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CONFIG1L (address:0x300000, mask:0x5D) |
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RETEN -- VREG Sleep Enable bit |
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RETEN = OFF |
0xFE |
Disabled - Controlled by SRETEN bit. |
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RETEN = ON |
0xFF |
Enabled. |
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INTOSCSEL -- LF-INTOSC Low-power Enable bit |
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INTOSCSEL = LOW |
0xFB |
LF-INTOSC in Low-power mode during Sleep. |
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INTOSCSEL = HIGH |
0xFF |
LF-INTOSC in High-power mode during Sleep. |
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SOSCSEL -- SOSC Power Selection and mode Configuration bits |
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SOSCSEL = LOW |
0xEF |
Low Power SOSC circuit selected. |
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SOSCSEL = DIG |
0xF7 |
Digital (SCLKI) mode. |
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SOSCSEL = HIGH |
0xFF |
High Power SOSC circuit selected. |
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XINST -- Extended Instruction Set |
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XINST = OFF |
0xBF |
Disabled. |
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XINST = ON |
0xFF |
Enabled. |
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CONFIG1H (address:0x300001, mask:0x08) |
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FOSC -- Oscillator |
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FOSC = LP |
0xF0 |
LP oscillator. |
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FOSC = XT |
0xF1 |
XT oscillator. |
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FOSC = HS2 |
0xF2 |
HS oscillator (High power, 16 MHz - 25 MHz). |
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FOSC = HS1 |
0xF3 |
HS oscillator (Medium power, 4 MHz - 16 MHz). |
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FOSC = EC3IO |
0xF4 |
EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz). |
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FOSC = EC3 |
0xF5 |
EC oscillator (High power, 16 MHz - 64 MHz). |
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FOSC = RC |
0xF6 |
External RC oscillator, CLKOUT function on OSC2. |
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FOSC = RCIO |
0xF7 |
External RC oscillator. |
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FOSC = INTIO2 |
0xF8 |
Internal RC oscillator. |
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FOSC = INTIO1 |
0xF9 |
Internal RC oscillator, CLKOUT function on OSC2. |
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FOSC = EC2IO |
0xFA |
EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 16 MHz). |
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FOSC = EC2 |
0xFB |
EC oscillator (Medium power, 160 kHz - 16 MHz). |
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FOSC = EC1IO |
0xFC |
EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz). |
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FOSC = EC1 |
0xFD |
EC oscillator (Low power, DC - 160 kHz). |
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PLLCFG -- PLL x4 Enable bit |
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PLLCFG = OFF |
0xEF |
Disabled. |
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PLLCFG = ON |
0xFF |
Enabled. |
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FCMEN -- Fail-Safe Clock Monitor |
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FCMEN = OFF |
0xBF |
Disabled. |
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FCMEN = ON |
0xFF |
Enabled. |
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IESO -- Internal External Oscillator Switch Over Mode |
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IESO = OFF |
0x7F |
Disabled. |
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IESO = ON |
0xFF |
Enabled. |
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CONFIG2L (address:0x300002, mask:0x7F) |
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PWRTEN -- Power Up Timer |
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PWRTEN = ON |
0xFE |
Enabled. |
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PWRTEN = OFF |
0xFF |
Disabled. |
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BOREN -- Brown Out Detect |
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BOREN = OFF |
0xF9 |
Disabled in hardware, SBOREN disabled. |
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BOREN = ON |
0xFB |
Controlled with SBOREN bit. |
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BOREN = NOSLP |
0xFD |
Enabled while active, disabled in SLEEP, SBOREN disabled. |
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BOREN = SBORDIS |
0xFF |
Enabled in hardware, SBOREN disabled. |
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BORV -- Brown-out Reset Voltage bits |
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BORV = 0 |
0xE7 |
3.0V. |
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BORV = 1 |
0xEF |
2.7V. |
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BORV = 2 |
0xF7 |
2.0V. |
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BORV = 3 |
0xFF |
1.8V. |
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BORPWR -- BORMV Power level |
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BORPWR = LOW |
0x9F |
BORMV set to low power level. |
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BORPWR = MEDIUM |
0xBF |
BORMV set to medium power level. |
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BORPWR = HIGH |
0xDF |
BORMV set to high power level. |
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BORPWR = ZPBORMV |
0xFF |
ZPBORMV instead of BORMV is selected. |
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CONFIG2H (address:0x300003, mask:0x7F) |
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WDTEN -- Watchdog Timer |
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WDTEN = OFF |
0xFC |
WDT disabled in hardware; SWDTEN bit disabled. |
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WDTEN = NOSLP |
0xFD |
WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled. |
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WDTEN = ON |
0xFE |
WDT controlled by SWDTEN bit setting. |
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WDTEN = SWDTDIS |
0xFF |
WDT enabled in hardware; SWDTEN bit disabled. |
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WDTPS -- Watchdog Postscaler |
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WDTPS = 1 |
0x83 |
1:1. |
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WDTPS = 2 |
0x87 |
1:2. |
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WDTPS = 4 |
0x8B |
1:4. |
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WDTPS = 8 |
0x8F |
1:8. |
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WDTPS = 16 |
0x93 |
1:16. |
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WDTPS = 32 |
0x97 |
1:32. |
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WDTPS = 64 |
0x9B |
1:64. |
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WDTPS = 128 |
0x9F |
1:128. |
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WDTPS = 256 |
0xA3 |
1:256. |
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WDTPS = 512 |
0xA7 |
1:512. |
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WDTPS = 1024 |
0xAB |
1:1024. |
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WDTPS = 2048 |
0xAF |
1:2048. |
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WDTPS = 4096 |
0xB3 |
1:4096. |
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WDTPS = 8192 |
0xB7 |
1:8192. |
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WDTPS = 16384 |
0xBB |
1:16384. |
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WDTPS = 32768 |
0xBF |
1:32768. |
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WDTPS = 65536 |
0xC3 |
1:65536. |
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WDTPS = 131072 |
0xC7 |
1:131072. |
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WDTPS = 262144 |
0xCB |
1:262144. |
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WDTPS = 524288 |
0xCF |
1:524288. |
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WDTPS = 1048576 |
0xFF |
1:1048576. |
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CONFIG3L (address:0x300004, mask:0x01) |
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RTCOSC -- RTCC Clock Select |
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RTCOSC = INTOSCREF |
0xFE |
RTCC uses INTRC. |
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RTCOSC = SOSCREF |
0xFF |
RTCC uses SOSC. |
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CONFIG3H (address:0x300005, mask:0x89) |
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CCP2MX -- CCP2 Mux |
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CCP2MX = PORTBE |
0xFE |
RE7-Microcontroller Mode/RB3-All other modes. |
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CCP2MX = PORTC |
0xFF |
RC1. |
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MSSPMSK -- MSSP address masking |
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MSSPMSK = MSK5 |
0xF7 |
5 bit address masking mode. |
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MSSPMSK = MSK7 |
0xFF |
7 Bit address masking mode. |
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MCLRE -- Master Clear Enable |
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MCLRE = OFF |
0x7F |
MCLR Disabled, RG5 Enabled. |
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MCLRE = ON |
0xFF |
MCLR Enabled, RG5 Disabled. |
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CONFIG4L (address:0x300006, mask:0x91) |
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STVREN -- Stack Overflow Reset |
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STVREN = OFF |
0xFE |
Disabled. |
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STVREN = ON |
0xFF |
Enabled. |
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BBSIZ -- Boot Block Size |
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BBSIZ = BB1K |
0xEF |
1K word Boot Block size. |
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BBSIZ = BB2K |
0xFF |
2K word Boot Block size. |
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DEBUG -- Background Debug |
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DEBUG = ON |
0x7F |
Enabled. |
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DEBUG = OFF |
0xFF |
Disabled. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Code Protect 00800-03FFF |
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CP0 = ON |
0xFE |
Enabled. |
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CP0 = OFF |
0xFF |
Disabled. |
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CP1 -- Code Protect 04000-07FFF |
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CP1 = ON |
0xFD |
Enabled. |
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CP1 = OFF |
0xFF |
Disabled. |
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CP2 -- Code Protect 08000-0BFFF |
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CP2 = ON |
0xFB |
Enabled. |
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CP2 = OFF |
0xFF |
Disabled. |
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CP3 -- Code Protect 0C000-0FFFF |
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CP3 = ON |
0xF7 |
Enabled. |
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CP3 = OFF |
0xFF |
Disabled. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Code Protect Boot |
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CPB = ON |
0xBF |
Enabled. |
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CPB = OFF |
0xFF |
Disabled. |
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CPD -- Data EE Read Protect |
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CPD = ON |
0x7F |
Enabled. |
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CPD = OFF |
0xFF |
Disabled. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Table Write Protect 00800-03FFF |
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WRT0 = ON |
0xFE |
Enabled. |
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WRT0 = OFF |
0xFF |
Disabled. |
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WRT1 -- Table Write Protect 04000-07FFF |
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WRT1 = ON |
0xFD |
Enabled. |
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WRT1 = OFF |
0xFF |
Disabled. |
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WRT2 -- Table Write Protect 08000-0BFFF |
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WRT2 = ON |
0xFB |
Enabled. |
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WRT2 = OFF |
0xFF |
Disabled. |
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WRT3 -- Table Write Protect 0C000-0FFFF |
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WRT3 = ON |
0xF7 |
Enabled. |
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WRT3 = OFF |
0xFF |
Disabled. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Config. Write Protect |
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WRTC = ON |
0xDF |
Enabled. |
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WRTC = OFF |
0xFF |
Disabled. |
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WRTB -- Table Write Protect Boot |
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WRTB = ON |
0xBF |
Enabled. |
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WRTB = OFF |
0xFF |
Disabled. |
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WRTD -- Data EE Write Protect |
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WRTD = ON |
0x7F |
Enabled. |
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WRTD = OFF |
0xFF |
Disabled. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBRT0 -- Table Read Protect 00800-03FFF |
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EBRT0 = ON |
0xFE |
Enabled. |
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EBRT0 = OFF |
0xFF |
Disabled. |
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EBRT1 -- Table Read Protect 04000-07FFF |
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EBRT1 = ON |
0xFD |
Enabled. |
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EBRT1 = OFF |
0xFF |
Disabled. |
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EBRT2 -- Table Read Protect 08000-0BFFF |
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EBRT2 = ON |
0xFB |
Enabled. |
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EBRT2 = OFF |
0xFF |
Disabled. |
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EBRT3 -- Table Read Protect 0C000-0FFFF |
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EBRT3 = ON |
0xF7 |
Enabled. |
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EBRT3 = OFF |
0xFF |
Disabled. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBRTB -- Table Read Protect Boot |
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EBRTB = ON |
0xBF |
Enabled. |
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EBRTB = OFF |
0xFF |
Disabled. |
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